The invention relates to defect detecting methods, and more particularly, to methods for wafer defect detection based on fail bit maps (MAP).
Semiconductor processes comprise integrated circuit (IC) designs, wafer fabrications, wafer probe tests, and wafer packaging. A wafer probe test probes each grain on a chip for testing electric characteristics. Failed grains are marked and discarded for preventing from increasing production cost.
The wafer probe test mainly locates defects on a chip. Conventionally, the wafer probe test implements tests related to electrical characteristics to all memory cells (disposed as a matrix) on a chip, displaying coordinates of failed memory cells in the form of fail bit mapping (FBM), according to test results, in a coordinate region defined by the X and Y axes, and estimating failed reasons according to analyzed FBM types, such as point-failed, block-failed, or line-failed. The fail bit mapping is an abnormal analysis method for semiconductor components, visualizing addresses of abnormal memory cells for confirmations.
Defect detections may be performed after wafer probe test are complete, raising yield rates of chips. FBM tests, for example, are first implemented, and defect detections, such as working voltage tests, wafer level burn-in (WLBI) tests, function tests, and the like, are then implemented. WLBI tests consider the decrease of production cost beforehand during the design stage. Reliability verification, for example, is considered in circuit design, such that a WLBI mode is involved to implement reliability verification to products in the wafer test stage and the products may not be burned after a package process, thereby decreasing package and finished product test costs.
The WLBI process can find failed bits on each chip and analyzes the chips with a greater number of failed bits for failed reasons. The WLBI process, however, may not discover failed bits each time. Some failed bits temporarily exist and each preformed defect test process may generate failed bits, such that it is difficult to determine which failed bit is produced at in which process. As described above, current solutions execute a FBM test again after all desired defect tests are complete. Thus, location information corresponding to failed bits is obtained in a last FBM test, and the current FBM test further verifies the location information.
The described solution, however, requires to perform a FBM test twice and further involves a WLBI test, spending and decreasing production capacity accordingly. Additionally, the described solution cannot accurately obtain location information of produced failed bits corresponding to each defect test. Thus, an improved method for locating failed bits is desirable, saving test time, raising product yield rates, and maintaining production capacity.